Under construction...

Interrupt Mappings

OpenPIC Interrupts

The OpenPIC in the Hydra supports up to 20 interrupt sources and up to 2 processors.

NumberSenseSource
0?SIOInt (Master 8259 Cascade)
10SCSI DMA
20SCC Tx A DMA
30SCC Rx A DMA
40SCC Tx B DMA
50SCC Rx B DMA
61SCSI device
71SCC A device
81SCC B device
91VIA
101ADB
110ADB_NMI
12?ExtInt1 (PCI #A)
13?ExtInt2 (PCI #B)
14?ExtInt3 (PCI #C)
15?ExtInt4 (PCI #D)
16?ExtInt5 (IDE)
17?ExtInt6
18?ExtInt7
19?Spare

Interrupt senses:

0
Postive Edge Triggered
1
Active Low Level

Legacy 8259 Interrupts

Master

NumberSenseSource
03Timer
138042
2?Slave 8259 Cascade
33Serial
43Serial
53Sound
63Floppy
73Parallel

Interrupt senses:

0
1
2
3

Slave

SenseNumberSource
0?
13MIDI
2?
3?
438042
5?
6?
7?

Interrupt senses:

0
1
2
3


This page is maintained by Geert Uytterhoeven.
$Date: 2006-01-25 21:24:49 $